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VeriSim

VeriSim

Advanced Logic Simulator

Digital Design Verification Constraint Solver Mixed Signal Verification Solution

VeriSim is an advanced logic simulator that offers a comprehensive digital design verification solution. 

  • Equipped with high-performance simulation engines and constraint solvers to enhance compile time efficiency for large SoC designs

  • Supports a wide array of languages, including Verilog, VHDL, SystemVerilog, SystemC, and their combinations

  • Integrates Universal Verification Methodology (UVM) to enable rapid verification testbench setup

  • Provides extensive features for function and code coverage testing

  • Assertion-based verification facilitates the early detection and rectification of potential design flaws, compressesing the verification timeline and expediting the time-to-market

  • Added security through encryption algorithms to safeguard customer IP

  • Integrates with transistor-level NanoSpice simulators to provide complete mixed signal verification solutions


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Highlights

  • High performance and capacity

    Innovated optimization from compilation,
    simulation to constraint solver engines

  • Advanced simulation technology

    X-state propagation and
    race condition elimination

  • Compatibility and usability

    Easy to use and quick migration
    from existing tools

  • Extensive
    computing architecture

    Supports both X86 and
    ARM platforms

  • One-stop mixed
    signal verification solution

    Native integration with NanoSpice
    for mixed signal verification

Applications

  • Digital circuits
    from behavioral,
    RTL to gate
    level with SDF

  • Mixed signal SoC
    full chip verification
    by integrating
    NanoSpice

  • SystemVerilog
    and SystemC
    mixed language
    testbench

  • Testbench
    setup
    in system
    verification

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